This invention relates to systems for processing data, and more particularly to a means for apportioning data from common sources among a plurality of memory banks contending for the data.
It is a known technique in data processing to provide a configuration involving a plurality of memory banks or other destinations connected in common to one or more sources of data. Typically, incoming data is provided serially to a parallel arrangement of such destinations, whereby in combination they are capable of processing or transferring data at a rate commensurate with the serial data supply rate.
such systems require means for apportioning incoming data among the contending destinations. One approach involves assigning individual, sequential priority to the destinations. For example, U.S. Pat. No. 3,534,339 (Rosenblatt) discloses a system which encodes identification bits of multiple active devices simultaneously, and selects the identification bits corresponding to a request signal from the highest priority device. Similarly, in U.S. Pat. No. 3,425,037 (Patterson), signals from all peripheral devices sharing a common connection are monitored, with a request signal from each inhibited if the monitoring means senses a higher priority request. Other direct sequential priority systems are disclosed in U.S. Pat. No. 4,745,548 (Blahut) and U.S. Pat. No. 3,353,160 (Lindquist).
Alternatively, priority can be determined by sensing the priority of less than all contending destinations. For example, U.S. Pat. No. 3,832,692 (Henzel) discloses a plurality of priority seeking devices sharing a common bus. Each device "looks back" in the sense of determining the priority indications of two or more previous, higher priority devices. Thus, access is permitted only if the previous two or more devices are not requesting access.
The aforementioned sequential systems, when employed in connection with competing destinations, tend to supply the majority of data to the highest priority destinations at the expense of the lowest priority destinations. This problem can be reduced by limiting the number of separate destinations sharing the common source of data, or by employing additional circuitry or logic to counter the effect of the unequal priorities. For example, U.S. Pat. No. 3,676,860 (Collier) discloses a system in which competing processors each have a request phase and a control phase, with a priority system determining which among several processors can move from the request to the control phase. A register which determines priorities is modified each time a connection is established by one of the processors. In U.S. Pat. No. 3,399,384 (Crockett), each of a plurality of peripheral devices can issue demand signals of differing priorities. Consequently, final priority is determined by the level of the request, and also by a preassigned priority among the peripheral devices.
Another approach to countering the unequal priorities is shown in U.S. Pat. No. 4,760,515 (Malmquist). A plurality of arbiters are assigned a sequential priority, with each arbiter enabled to access a shared bus if no access requests are received from higher priority arbiters. A command rotor is provided to determine priority among plural requests simultaneously reaching the same arbiter. In U.S. Pat. No. 3,742,148 (Ledeen), sequentially arranged stations are connected to a common terminal, with each station having control circuitry interconnected with at least two other stations. In particular, control circuitry of a given station is connected to the next succeeding and to the next preceding stations. When conditioned to transmit, or when disabled by the next preceding station, the given station disables the succeeding station. The given station also can be disabled by the next succeeding station, in which case the control circuitry also disables the next preceding station.
To the extent that certain of these approaches tend to equalize the usage of the contending data destinations, they either tend to be overly complex, or fail to achieve a satisfactory degree of equality.
Therefore, it is an object of the present invention to improve the rate at which memory banks can be initiated for receiving serial data, while providing substantially equal usage of all banks.
Another object of the invention is to improve memory performance by issuing a bank request at the clock cycle rate, eliminating lost clock cycles between bank requests.
Another object is to inmate a bank function at a designated clock cycle rate, even if certain bank requests in a predetermined priority scheme are bypassed.
Yet another object is to increase the speed of operation of memory bank priority logic, by eliminating conventional scanning techniques which waste clock cycles on bank rotation regardless of the request status of the banks.